1. Field of the Invention
The present invention relates to a clock extracting circuit adapted for use in a playback unit of a data recorder or the like to extract clock pulses included in input data transmitted by a self-clocking system.
2. Description of the Prior Art
In a data recorder for recording desired information data on a magnetic tape and reproducing the recorded data therefrom, it is generally customary to employ a self-clocking data transmission system which records modulated information data inclusive of clock pulses on a magnetic tape and, in a playback mode, extracts the clock pulses included in the reproduced digital signal. According to such system, the information data is obtained by demodulating the reproduced digital signal in conformity with the clock pulses.
More specifically, in a data playback unit 1 of a data recorder shown in FIG. 2, information data recorded on a magnetic tape 2 is reproduced therefrom by means of a head 3 and then is inputted as a reproduced RF signal S.sub.RF via a head amplifier 4 and an equalizer 5 to a binary encoder 6 having a comparator circuit configuration.
A predetermined reference voltage V.sub.REF is applied to the binary encoder 6 for converting the reproduced RF signal S.sub.RF into a binary value in accordance with the level of the reference voltage V.sub.REF to thereby obtain input data DT.sub.IN, which is then supplied to an input terminal D of a D flip-flop 7 while being supplied also to a clock extracting circuit 8.
As a result, the clock extracting circuit 8 extracts clock pulses CK synchronized with the input data DT.sub.IN and feeds the extracted clock pulses CK to a clock terminal of the D flip-flop 7 while supplying the same also to an unshown digital signal processing circuit in a stage posterior thereto.
The D flip-flop 7 synchronizes the input data DT.sub.IN at the timing coincident with the clock pulses CK and then transmits the resultant input data DT.sub.IN1 to the digital signal processing circuit.
Subsequently the digital signal processing circuit executes demodulation of the input data DT.sub.IN1 in accordance with the timing of the clock pulses to thereby reproduce the information data.
As shown in FIG. 3, the conventional clock extracting circuit 8 is composed of a phase-locked loop (PLL) which comprises a data window generator 9, a phase comparator 10, a voltage-controlled oscillator (VCO) 11 and a low-pass filter (LPF) 12.
Practically, the input data DT.sub.IN (FIG. 4 (A)) is supplied to the data window generator 9, which then generates data window pulses DT.sub.WD (FIG. 4 (B)) having a predetermined duration and rising in synchronism with the leading edge and trailing edge of the input data DT.sub.IN. Such data window pulses DT.sub.WD are inputted to the phase comparator 10.
The phase comparator 10 is supplied also with clock pulses CK (FIG. 4 (C)) which are substantially similar to the clock pulses generated by the VCO 11 and included in the input data DT.sub.IN.
The phase comparator 10 generates an error voltage V.sub.ER1 where each clock pulse CK rises in synchronism with a center instant t.sub.1 in the duration (between instants t.sub.0 and t.sub.2) of the data window pulse DT.sub.WD. The error voltage V.sub.ER1 thus obtained is averaged via the LPF 12 to produce an average error voltage V.sub.ER2, which is then used for controlling the oscillation frequency of the VCO 11.
In this manner, the clock extracting circuit 8 extracts the clock pulses CK synchronized in phase with the clock pulses included in the input data DT.sub.IN, and then transmits such extracted clock pulses CK.
As shown in FIG. 5, the data window generator 9 comprises a delay circuit and an exclusive OR circuit 9B, wherein the delay circuit consists of a resistor R1, a capacitor C1 and an amplifier 9A. The data window generator 9 executes an exclusive OR operation between the input data DT.sub.IN and the data DT.sub.IND delayed for a predetermined time, thereby generating a data window pulse DT.sub.WD.
The phase comparator 10 is so composed as shown in FIG. 6, wherein a first current source 10A, a first switch SW.sub.A, a second switch SW.sub.B and a second current source 10B are connected in series to one another between a power source V.sub.CC and the ground, and the junction of the first and second switches SW.sub.A and SW.sub.B is grounded via a capacitor C2 while being connected to an amplifier 10C so that an error voltage V.sub.ER1 is outputted therethrough.
Practically, in the phase comparator 10, first and second switch control signals CNT.sub.A and CNT.sub.B are generated in accordance with the data window pulse DT.sub.WD and the clock pulse CK, and the first and second switches SW.sub.A and SW.sub.B are selectively controlled by such signals to execute a phase comparison.
More specifically, the first and second switches SW.sub.A and SW.sub.B are controlled by the first and second switch control signals CNT.sub.A and CNT.sub.B in such a manner as to be held in an off-state during the time period where the data window pulse DT.sub.WD has a logical low level.
Meanwhile, during the time period (e.g., between instants t.sub.0 and t.sub.1) where the data window pulse DT.sub.WD has a logical high level and the clock pulse CK has a logical low level, the first switch SW.sub.A alone is held in an on-state to thereby charge the capacitor C2.
Furthermore, during the time period (e.g., between instants t.sub.1 and t.sub.2) where both the data window pulse DT.sub.WD and the clock pulse CK have a logical high level, the first switch SW.sub.A is held in an off-state while the second switch SW.sub.B is held in an on-state to thereby discharge the capacitor C2.
Thus, when the clock pulse CK and the data window pulse DT.sub.WD are coincident in phase with each other and the leading edge of the clock pulse CK is synchronous with the center instant of the high-level duration of the data window pulse DT.sub.WD, the charge time and the discharge time of the capacitor C2 are mutually equal so that an error voltage V.sub.ER1 of a value "0" is outputted via the amplifier 10C.
To the contrary, if the clock pulse CK and the window pulse DT.sub.WD have a phase deviation from each other, the charge time and the discharge time of the capacitor C2 are rendered unbalanced to consequently cause a variation in the average voltage across the capacitor C2, whereby an error voltage V.sub.ER1 of a value corresponding to such voltage variation is outputted via the amplifier 10C.
In the clock extracting circuit 8, as described above, a control action is so performed that the clock pulse CK rises in synchronism with the center instant of the high-level duration of the data window pulse DT.sub.WD, and therefore the clock pulses CK coincident in phase with the clock pulses included in the input data DT.sub.IN can be transmitted.
In the data playback unit 1 of the constitution mentioned, there is known an example where both the transport speed of a magnetic tape 2 and the rotational speed of a drum with a head 3 mounted thereon are so controlled as to maintain the relative speed of the head 3 to the magnetic tape 2 in the recording track direction, and the transmission rate of the input data DT.sub.IN is changed under such condition from a standard rate of 1/1 speed to a lower rate of 1/2, 1/4, 1/8, 1/16 or 1/24 speed.
Suppose now that the transmission rate of the input data DT.sub.IN is changed from a 1/1 speed to a 1/2 speed for example. In case the input data DT.sub.IN transmitted at a 1/2 speed is to be locked by the high-level duration of the data window pulse WT.sub.IN conforming with a 1/1 speed, the charge and discharge of the capacitor C2 fail to be performed completely since the number of high-level pulses of the data window DT.sub.WD within a unitary time is reduced to 1/2, and therefore the time required for the PLL to be locked is rendered longer to consequently bring about a problem that the stability is deteriorated.